Description
The IEEE Student Branch RRU under SASET in collaboration with
PrimeMOS Research & Solutions offers this 5-day primer to equip participants with practical, hands-on skills in Very Large- Scale Integration (VLSI) Design. Essential concepts such as Tool Installation & Environment Setup, Analog & Transistor-Level Digital Design (LTspice), RTL Design & Synthesis (Verilog + Vivado), the complete RTL-to-GDSII Flow (OpenLane), and Physical Design will be covered; these skills are directly applicable to semiconductor engineering, hardware security, and advanced technology research.
What you'll learn
VLSI Fundamentals
Master RTL Design
Design Circuits with LTspice
Execute RTL-to-GDSII Flows
Requirements
- Basic of Digital Electronics
- Network Analysis
Course Content
Semester with subjects
No Semester Founds.
Experts
P V S D D Mallikarjuna
VLSI Designer
Founder of PrimeMOS Research & Solutions and an Associate Member of IETE. As a research-driven VLSI engineer and semiconductor innovator, he specializes in CMOS and Digital IC Design with extensive expertise in industry-standard tools like Cadence Virtuoso, Xilinx Vivado, OpenLane, and the SkyWater PDK. An IEEE-published researcher and former Defense Research and Development Laboratory (DRDL) intern, he is currently pursuing a specialization in AI-Enabled VLSI Design. He is deeply passionate about educational democratization, mentoring aspiring electronics students in chip design, and exploring advanced research collaborations.
prathiksha sv 22 Aug, 2026
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prathiksha sv 22 Aug, 2026
Good
Nice